NCT7491
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Table 31. REGISTER TABLES
Address
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Description
R/W
0x1D9 
0x1DF
Reserved
0x1E0
R/W
Fuse Reg 1
7
6
5
4
3
2
1
0
0x1E1
R/W
Fuse Reg 2
7
6
5
4
3
2
1
0
0x1E2
R/W
Fuse Reg 3
7
6
5
4
3
2
1
0
0x1E3
R/W
Fuse Reg 4
7
6
5
4
3
2
1
0
0x1e4
R/W
Fuse Reg 5
7
6
5
4
3
2
1
0
0x1E5
R/W
Fuse Reg 6
7
6
5
4
3
2
1
0
0x1E6
R/W
Fuse Reg 7
7
6
5
4
3
2
1
0
0x1E7
R/W
Fuse Reg 8
7
6
5
4
3
2
1
0
0x1E8
R/W
Fuse Reg 9
7
6
5
4
3
2
1
0
0x1E9
R/W
Fuse Reg 10
7
6
5
4
3
2
1
0
0x1EA
R/W
Fuse Reg 11
7
6
5
4
3
2
1
0
0x1EB
R/W
Fuse Reg 12
7
6
5
4
3
2
1
0
0x1FF
R/W
Page Select Clear
RGMPCL
Table 32. PECI ADDRESS REGISTERS (Note 1) (PowerOn Default = 0x00)
Register Address
R/W
Description
0x00
R/W
PECI0 CPU Address
0x01
R/W
PECI1 CPU Address
0x02
R/W
PECI2 CPU Address
0x03
R/W
PECI3 CPU Address
1.  These registers are automatically populated when the PECI interface is enabled. They can be overwritten if necessary.
Table 33. PECI_Abs REGISTERS (Note 2) (PowerOn Default = 0x00)
Register Address
R/W
Description
0x04
R/W
PECI0 absolute value. 8 bit unsigned.
0x05
R/W
PECI1 absolute value. 8 bit unsigned.
0x06
R/W
PECI2 absolute value. 8 bit unsigned.
0x07
R/W
PECI3 absolute value. 8 bit unsigned.
2.  These registers return the absolute CPU temperature calculated using the Tjmax value for each PECI channel.
Table 34. PECI Tcontrol LIMIT REGISTERS (Note 3) (PowerOn Default = 0x00)
Register Address
R/W
Description
0x3D
R/W
PECI0 Tcontrol
0x08
R/W
PECI1 Tcontrol
0x09
R/W
PECI2 Tcontrol
0x0A
R/W
PECI3 Tcontrol
3.  If any PECI reading exceeds its T
CONTROL
 limit, all PWM outputs drive their fans at 100% duty cycle. This is a failsafe mechanism
incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software
or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below T
CONTRO
limit  hysteresis.
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